第6章 Impact of Si Processing

考试要会什么

本章对应 Lecture 6。它的核心不是讲完整晶圆工艺，而是回答：Si processing 的变化如何改变 packaging 的要求。

高频关键词：

• CMOS / MEMS / MOEMS；
• low-k ILD；
• die thinning；
• interposer；
• through-silicon via (TSV)；
• 3D integration。

一句话记忆

芯片工艺越先进，封装越要处理更脆弱的材料、更高 I/O、更薄 die、更强热/机械耦合。

Low-k ILD

Low-k interlayer dielectric 的优势是降低 on-chip interconnect parasitic capacitance，从而改善 delay 和 power。但 low-k 材料通常机械强度较弱、易受应力和加工影响。

答题重点：low-k improves electrical performance but creates packaging reliability challenges because fragile dielectric layers are sensitive to mechanical and thermal stresses.

Die thinning

Die thinning 的潜在好处：

• reduce package height；
• reduce thermal resistance；
• improve heat spreading path；
• enable stacking / 3D packaging；
• reduce form factor for portable products。

挑战：

• thin die is fragile；
• handling and warpage risk increase；
• CTE mismatch stress may become more serious；
• assembly process control becomes harder。

Interposer and TSV

Interposer 是位于 die 和 substrate/board 之间的 bridge/conduit，用于重新分配信号、连接多个 die 或实现高密度互连。

TSV 是穿过 silicon wafer/die 的垂直互连。它用于 3D IC 和高密度封装，可缩短互连长度，提高带宽和集成密度。

技术	作用	优势	挑战
Interposer	bridge / redistribution between dies and substrate	high-density routing, heterogeneous integration	cost, thermal, CTE/stress
TSV	vertical via through silicon	short interconnect, 3D stacking, high bandwidth	process complexity, thermal stress, yield
Die thinning	thinner die for stacking and thermal path	lower height, lower thermal resistance	fragility, warpage, handling

题型模板

题型：What is the impact of Si processing on packaging?

1. Si processing enables CMOS, MEMS and advanced microsystems。
2. Scaling and interconnect development increase I/O density and performance demand。
3. Low-k ILD reduces parasitic capacitance but introduces fragile materials。
4. Die thinning and 3D integration reduce size and interconnect length but increase mechanical/thermal stress。
5. Packaging must provide reliable interconnection, thermal management and stress control。

易错点

• 不要把 low-k 只写成“好材料”，它的 packaging challenge 同样重要。
• TSV 不是普通 wire，它是 vertical through-silicon interconnect。
• Interposer 的关键词是 bridge、redistribution、multi-die integration。

本章概览

Lecture 6 不要求你复述完整 wafer fabrication，而是要求你说明：Si processing 的发展如何改变 package 的压力。关键词包括 feature size、interconnect density、low-k ILD、die thinning、MEMS/MOEMS、TSV/interposer。

零基础先览

• CMOS scaling：让 chip 更快更复杂，但 I/O 和 heat density 上升。
• Low-k ILD：降低 capacitance，但材料机械强度较弱。
• Die thinning：让封装更薄、热阻更低、可堆叠，但 die 更脆。
• Interposer：在 die 和 substrate 之间做 bridge/redistribution。
• TSV：穿过 silicon 的垂直互连，用于 3D package。

Si processing 对 packaging 的影响链

smaller feature size / more functions
→ higher I/O and power density
→ shorter interconnect and better thermal path needed
→ advanced package: flip-chip, interposer, TSV, SiP, WLP
→ new reliability risks: low-k cracking, die warpage, thermal stress, yield loss

Low-k ILD 深入理解

Low-k dielectric 的目的：降低 interconnect capacitance。因为 RC delay 和 dynamic power 与 capacitance 有关，low-k 有利于 electrical performance。

但对 package 来说，它带来新的问题：

• lower mechanical strength；
• lower fracture toughness；
• more sensitive to packaging stress；
• risk of delamination or cracking during assembly/thermal cycling。

高分句：

Low-k ILD improves on-chip electrical performance by reducing parasitic capacitance, but it increases packaging reliability challenges because the dielectric is mechanically fragile and sensitive to assembly-induced stress.

Die thinning 深入理解

Die thinning 的目的不是单纯“磨薄”，而是服务 advanced packaging：

Benefit	Reason
Lower package height	thinner die allows thinner product
Better thermal path	shorter conduction path through silicon
3D stacking	thin dies are easier to stack
Lower stress in some structures	reduced stiffness may help certain assemblies

但同时：

• thin die cracks more easily；
• warpage and handling risk increase；
• die attach and pick-place more difficult；
• CTE mismatch stress control becomes more important。

Interposer / TSV / 3D integration

Interposer 可以理解为 high-density bridge。它让多个 die 通过 fine-pitch routing 互连，再连接到 package substrate。TSV 则提供 through-silicon vertical path，使 3D stack 中上下 die 可以短距离连接。

考试比较时可写：

Technology	It solves	It creates
Interposer	routing density and heterogeneous die integration	cost, thermal path, extra interface
TSV	vertical high-density interconnect	process complexity, stress, yield
3D stacking	small footprint, high bandwidth	heat removal and testing difficulty

标准答案：impact of Si processing

The impact of Si processing on microelectronic packaging is that advances in wafer fabrication produce smaller, faster and more highly integrated chips, which require packages with higher I/O density, shorter interconnects, better power delivery and better thermal management. Low-k ILD reduces parasitic capacitance but is mechanically fragile. Die thinning reduces package height and thermal resistance but increases handling and stress risk. TSVs and interposers enable 3D and heterogeneous integration, but they introduce new thermal, stress, yield and cost challenges.

Self-check

• low-k 是否同时写 benefit 和 reliability challenge？
• die thinning 是否同时写 package height/thermal 和 fragility？
• TSV 是否写 vertical interconnect，而不是普通 via？
• interposer 是否写 bridge/redistribution/multi-die？

Reference

• Lecture 6: impact of Si processing, low-k ILD, die thinning, MEMS/MOEMS, TSV/interposer。
• 考前一小时.docx 和学长 L5/L6：low-k ILD、die thinning、TSV/interposer 高频提示。

来源说明

Slides-backed: Lecture 6。Exam-signal: 考前一小时.docx、学长 L5/L6 整理多次出现 low-k ILD、die thinning、TSV、interposer。