第10章 Question and Answer Templates

考试要会什么

• 看到 explain / discuss / compare / with figures，能立刻判断该套哪一种答题骨架。
• 能把 packaging function、technology waves、CTE、thermal、SoC/SiP、wire bonding/TAB/flip-chip、WLP 等高频题写成完整段落。
• 能在答案里同时写出 definition、mechanism、impact、limitation 和 example，而不是只堆关键词。

一句话记忆

模板不是背作文，而是保证每道大题都有“定义 + 机制 + 影响 + 缺点/限制 + 图示/例子”这五块。

用法

本章不是新知识，而是考试时可直接套用的答题框架。遇到不会写的题，先把题目归类到下面模板。

Template 1：Explain why packaging is important

Microelectronics packaging is important because it provides the bridge between a fragile semiconductor die and a usable electronic system. It provides signal interconnection, power and ground distribution, heat dissipation, mechanical support and environmental protection. As ICs become smaller, faster and more power-dense, packaging increasingly controls system performance, reliability and cost.

可展开维度：signal、power、heat、mechanical、environment、cost。

Template 2：Trace technology waves

句子位置	写什么
1	Microelectronics packaging evolved to meet increasing I/O density, miniaturization and performance demand.
2	Through-hole/DIP was simple and robust but large and low-density.
3	SMT reduced size and increased board density but peripheral leads limited I/O.
4	BGA/CSP/flip-chip enabled area-array and shorter interconnects but introduced solder reliability and inspection challenges.
5	Advanced 2.5D/3D/SiP/FOWLP enables heterogeneous integration but creates thermal, yield and cost challenges.

Template 3：Compare two technologies

比较题用固定五维：

1. Definition / structure。
2. Electrical performance。
3. Cost and equipment。
4. Reliability / thermal / mechanical issue。
5. Suitable applications。

Example: wire bonding vs flip-chip

维度	Wire bonding	Flip-chip
Structure	wires from die pads to leads/substrate	solder bumps directly connect die to substrate
Cost	low, mature	higher due to bumping/substrate/process
Electrical	long wires, higher parasitics	short path, better high-speed performance
I/O density	peripheral, limited	area-array, high density
Reliability	mature but wire sweep/bond failure	needs underfill; solder fatigue concern

Template 4：Explain a failure mechanism

适用于 CTE、moisture、thermal cycling、solder fatigue。

1. Define the driving factor。
2. Explain where it appears in the package。
3. Explain the physical mechanism。
4. Name the failure mode。
5. Give mitigation.

Example: CTE mismatch

CTE mismatch means different materials expand by different amounts for the same temperature change. In a package, silicon, solder, substrate and board often have different CTE values. During thermal cycling, this mismatch generates shear stress at solder joints and interfaces, leading to fatigue cracks, delamination or die cracking. It can be mitigated by material matching, underfill and careful mechanical design.

Template 5：Thermal calculation

1. 写出 heat source / power dissipation。
2. 判断 heat transfer mode：conduction / convection / radiation。
3. 写公式和单位。
4. 若两面散热，面积用 total exposed area。
5. 得出 temperature rise 或 heat dissipation。

常用公式：

$$R_\theta=\frac{\Delta T}{P},\quad Q=\frac{kA\Delta T}{L},\quad Q=hA(T_s-T_f)$$

Template 6：Explain WLP advantage and challenge

WLP is attractive because packaging operations are performed at wafer level, so many dies are processed in parallel before singulation. This reduces handling, assembly time and cost, while also giving a small form factor and short interconnects. However, WLP is limited by die area, ball pitch, PWB routing capability and solder joint fatigue under thermal cycling.

高频答案库

Q1. Explain why systems packaging is multidisciplinary

Systems packaging is multidisciplinary because it must solve electrical, mechanical, thermal and materials problems at the same time. Electrically, it provides signal paths and power/ground distribution while controlling parasitic resistance, inductance and capacitance. Mechanically, it supports the fragile die and protects interconnects against shock, vibration and stress. Thermally, it removes heat from the device to the ambient. From a materials perspective, it must select compatible metals, polymers, ceramics, solders, underfills and substrates with suitable CTE, thermal conductivity and moisture resistance. Therefore packaging requires electrical, mechanical and materials engineering to achieve reliable system-level operation.

Q2. Discuss future developments and challenges

Future microelectronics packaging will move toward higher density, smaller form factor and heterogeneous integration. Important trends include 2.5D/3D integration using interposers and TSVs, chiplet-based SiP, fan-out wafer-level packaging, embedded die technologies and advanced thermal solutions. These technologies reduce interconnect length, improve bandwidth and allow different process technologies to be combined. However, they also create challenges in heat removal, CTE mismatch, warpage, solder fatigue, fine-pitch routing, testing, yield and manufacturing cost.

Q3. Explain role of underfill

Underfill is a polymer material placed between a flip-chip die and the substrate. Its main purpose is to mechanically couple the die and substrate so that thermal cycling stress is shared over a larger area rather than concentrated in solder bumps. It improves solder joint fatigue life and protects the interconnects from moisture and contamination. However, poor underfill process may introduce voids or delamination.

Q4. Explain why thermal management is critical

Thermal management is critical because power dissipated in microelectronic devices becomes heat. Excessive temperature can degrade semiconductor performance, accelerate failure mechanisms and cause catastrophic package failure such as cracking, delamination or melting. A good package provides a low-resistance heat path through die attach, TIM, substrate, heat spreader and heat sink to the ambient.

Q5. Compare WLP and wire bonding

Wire bonding connects each die pad to package leads using individual metal wires. It is mature and low cost, but it is a serial process with long interconnects and limited I/O density. WLP performs packaging operations at wafer level before dicing, processing many dies in parallel. This reduces handling, package size and interconnect length, but it faces fine-pitch routing, limited I/O count and solder fatigue challenges.

中文速写模板

如果考试允许中英混合，中文组织可以这样写：

定义：X 是……
作用：它用于解决……
机制：原因是……，因此会……
优点：从 cost / electrical / thermal / reliability 看……
缺点：但它会带来……
结论：所以 X 适合……，不适合……

画图题最低配置

Package hierarchy

画：die → package → PWB → system。标：signal、power、heat、mechanical support、protection。

CTE mismatch

画：die 在上、substrate/board 在下、中间 solder balls。标：board expansion larger、solder shear、fatigue crack。

Heat path

画：die → TIM → heat spreader/sink → ambient。标：conduction、interface resistance、convection。

Interconnect comparison

画三栏：wire bonding 弧形线、TAB tape lead、flip-chip bumps。标：cost/flexibility vs short path/high I/O。

Reference

本章综合 practice questions、Exam paper 2022、Lecture 1-9 和 senior notes，目标是提供可直接背诵和变形的 answer skeleton。

来源说明

本章综合 M01-M08 中的问答和主线 Lecture 1-9。正式表述以 slides-backed concepts 为基础，practice 只决定答题结构。